{"title":"基于0.35um AMS技术的1GHz负对数函数的实现","authors":"W. Ruan","doi":"10.1109/ISISE.2010.111","DOIUrl":null,"url":null,"abstract":"This paper presents the realization of the 1GHz Negative Logarithmic Function (NLF) based on the 0.35um AMS technology. Firstly, it shows some interesting advance beyond Mitchell's approach with hardware implementation of a sequential architecture minimized in terms of gates and thus optimized for power and area sensitive application. Secondly, it introduces the realization of the NLF using combinational logic only. Lastly, it presents the realization of the physical layout using the second method based on 0.35um AMS technology with Silicon Ensemble software.","PeriodicalId":206833,"journal":{"name":"2010 Third International Symposium on Information Science and Engineering","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The Realization of the 1GHz Negative Logarithmic Function Based on the 0.35um AMS Technology\",\"authors\":\"W. Ruan\",\"doi\":\"10.1109/ISISE.2010.111\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the realization of the 1GHz Negative Logarithmic Function (NLF) based on the 0.35um AMS technology. Firstly, it shows some interesting advance beyond Mitchell's approach with hardware implementation of a sequential architecture minimized in terms of gates and thus optimized for power and area sensitive application. Secondly, it introduces the realization of the NLF using combinational logic only. Lastly, it presents the realization of the physical layout using the second method based on 0.35um AMS technology with Silicon Ensemble software.\",\"PeriodicalId\":206833,\"journal\":{\"name\":\"2010 Third International Symposium on Information Science and Engineering\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Third International Symposium on Information Science and Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISISE.2010.111\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Third International Symposium on Information Science and Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISISE.2010.111","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Realization of the 1GHz Negative Logarithmic Function Based on the 0.35um AMS Technology
This paper presents the realization of the 1GHz Negative Logarithmic Function (NLF) based on the 0.35um AMS technology. Firstly, it shows some interesting advance beyond Mitchell's approach with hardware implementation of a sequential architecture minimized in terms of gates and thus optimized for power and area sensitive application. Secondly, it introduces the realization of the NLF using combinational logic only. Lastly, it presents the realization of the physical layout using the second method based on 0.35um AMS technology with Silicon Ensemble software.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
