Performance Analysis of a Double-Gate Junctionless Transistor with Varied Doping and Gate Underlap using Device Simulator

In this work, the impact of doping concentrations and gate underlap towards the electrical performance of a double-gate junctionless transistor (DG-JLT) were investigated using three-dimensional device simulator. The results show that the parameter of doping concentrations (Nd) has a greater impact towards the electrical performance of the transistor as compared to the gate underlap length (Lun). This can be seen in the results of leakage current (Ioff) and Drain-Induced Barrier Lowering (DIBL), where variations in Nd causes differences as high as 5 decades to be obtained for Ioff together with significant increase in DIBL. In overall, it was found that Nd=1×10¹⁸ cm^-3 provides the best results in terms of the lowest DIBL and Ioff and the highest Ion/Ioff ratio. Meanwhile, longer Lun is found to give better electrical characteristics. The results obtained in this work can be used to further determine the most significant factors among the structural and material parameters that influence the electrical characteristics of a JLT.