FT-LFSR: A Fault Tolerant Architecture for Linear Feedback Shift Registers

Linear Feedback Shift Registers (LFSR) are extensively used in variety of applications such as Built-In-Self-Test circuits or Pseudo Random Number Generators. Hence, fault tolerant design of LFSR is essential for the applications with high reliability demands. Traditional fault tolerant LFSRs include large number of Single-Point-of-Failures (SPoFs) in which any fault results in the whole system failure. In this paper, a new fault tolerant architecture for LFSR (named as FT-LFSR) is proposed in which the number of SPoFs are significantly reduced compared to the previous ones. To this end, a modified version of Triple Modular Redundancy (TMR) empowered with some extra controlling units for identifying the operational module is used. In addition, a novel metric called Reliability-Area-Factor (RAF) is introduced to evaluate the efficacy of the redundancy-based fault tolerant techniques (such as FT-LFSR) in terms of number of SPoFs and the area overhead. Experimental results show that, the FT-LFSR is resilient to all single transient and permanent faults except in its limited SPoFs and many patterns of multiple faults.