具有输入和输出队列的宽带分组交换体系结构

Chih-Yuan Chang, A. Paulraj, T. Kailath
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引用次数: 25

摘要

ATM是B-ISDN最有前途的解决方案之一。基于Batcher-banyan网络的交换机架构被认为最适合构建大维度宽带分组交换机。虽然Batcher-banyan网络内部是无阻塞的,但由于出口冲突导致的丢包问题无处不在,只能通过外部缓冲来减少。缓冲策略基本上分为两类:输入缓冲和输出缓冲。对于输入缓冲开关,一种称为线路头阻塞(HOL)的现象将最大吞吐量限制在58.6% (2-/spl基数/2)。另一方面,输出缓冲实现了高得多的吞吐量,但是整个交换机必须以足够高的速度运行,以便同时将所有数据包发送到同一个出口。这通常会造成严重的执行问题。我们提出了一种结合输入和输出队列的交换架构。交换结构由一个Batcher排序网络、一个基数-r shuffle映射网络和r个并行分布模块组成。输入队列和交换结构以与输入和输出中继相同的速度运行。然而,在单个时隙中,可能有多达r个数据包到达输出队列。我们分析了所提出的交换机的吞吐量-延迟特性。在r=2的情况下,最大吞吐量为88.6%。对于r=4,建议的交换机提供99.6%的最大吞吐量。此外,提议的交换机通过允许在一个时隙内将多达r个数据包发送到同一出口来缓解HOL阻塞。因此,平均延迟也减少了。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A broadband packet switch architecture with input and output queueing
The ATM is one of the most promising solutions for B-ISDN. Switch architectures based on Batcher-banyan networks are considered the most suitable for constructing large-dimension broadband packet switches. Though the Batcher-banyan network is internally nonblocking, the ubiquitous problem of packet loss resulting from outlet conflict can only be reduced by external buffering. Buffering strategies are basically categorized into two classes: input buffering and output buffering. For input-buffered switches, a phenomenon called head-of-the-line (HOL) blocking limits the maximum throughput to only 58.6 percent (2-/spl radic/2). On the other hand, output buffering achieves much higher throughput, but the entire switch has to be operated at a sufficiently high speed in order to deliver all the packets simultaneously destined for the same outlet. This generally imposes severe implementation problems. We propose a switch architecture with combined input and output queueing. The switch fabric consists of a Batcher sorting network, a radix-r shuffle mapping network, and r parallel distributing modules. The input queues and the switch fabric run at the same speed as the input and output trunks. However, up to r packets may arrive at an output queue in a single time slot. We analyze the throughput-delay characteristics of the proposed switch. The maximum throughput in the case where r=2 is 88.6 percent. For r=4, the proposed switch offers a 99.6 percent maximum throughput. In addition, the proposed switch relieves the HOL blocking by allowing up to r packets to be delivered to the same outlet in one time slot. Consequently, the average delay is also reduced.
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