Area Efficient Approximate 4–2 Compressor for Multiplier Design

In many applications like Digital Signal Processing (DSP), the multiplier is the basic building block, which uses the more complex circuitry. As the DSP applications are tolerable to outputs with some error, the replacement of exact multiplier with approximate multiplier gives the higher energy efficiency. In this paper a new approximate 4–2 compressor circuit is proposed for less complex multiplication process. The proposed compressor uses less hardware circuitry and less energy. The simulation results shows that the approximate multiplier by using the proposed approximate 4–2 compressor consumes less energy when compared with other multipliers with bit size of 8×8. The proposed multiplier gives 77.94% reduction in EDP when compared with the exact multiplier.