{"title":"一种可扩展的共享缓冲ATM交换机的FPGA实现","authors":"J. W. Shim, G. Jeong, M.K. Lee","doi":"10.1109/ICATM.1998.688184","DOIUrl":null,"url":null,"abstract":"This paper describes the architecture of a scalable shared buffer ATM switch and FPGA (field programmable gate array) implementation. The proposed ATM switch has a 2-D array of sub-memory blocks as a shared buffer. We can enlarge the buffer capacity by increasing the array size without any change of circuit. The prototype switch has been designed for a 4/spl times/4 ATM switch which has a shared buffer for 32 16-byte cells and implemented using FPGA to verify its function. The operating frequency of the designed test-bed is 40 MHz.","PeriodicalId":257298,"journal":{"name":"1998 1st IEEE International Conference on ATM. ICATM'98","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"FPGA implementation of a scalable shared buffer ATM switch\",\"authors\":\"J. W. Shim, G. Jeong, M.K. Lee\",\"doi\":\"10.1109/ICATM.1998.688184\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the architecture of a scalable shared buffer ATM switch and FPGA (field programmable gate array) implementation. The proposed ATM switch has a 2-D array of sub-memory blocks as a shared buffer. We can enlarge the buffer capacity by increasing the array size without any change of circuit. The prototype switch has been designed for a 4/spl times/4 ATM switch which has a shared buffer for 32 16-byte cells and implemented using FPGA to verify its function. The operating frequency of the designed test-bed is 40 MHz.\",\"PeriodicalId\":257298,\"journal\":{\"name\":\"1998 1st IEEE International Conference on ATM. ICATM'98\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 1st IEEE International Conference on ATM. ICATM'98\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICATM.1998.688184\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 1st IEEE International Conference on ATM. ICATM'98","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICATM.1998.688184","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA implementation of a scalable shared buffer ATM switch
This paper describes the architecture of a scalable shared buffer ATM switch and FPGA (field programmable gate array) implementation. The proposed ATM switch has a 2-D array of sub-memory blocks as a shared buffer. We can enlarge the buffer capacity by increasing the array size without any change of circuit. The prototype switch has been designed for a 4/spl times/4 ATM switch which has a shared buffer for 32 16-byte cells and implemented using FPGA to verify its function. The operating frequency of the designed test-bed is 40 MHz.
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