基于SystemBuilder的MPEG4解码器设计实例研究

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI:10.1109/VDAT.2009.5158168

S. Shibata, S. Honda, H. Tomiyama, H. Takada

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引用次数: 3

摘要

本文介绍了一个使用系统级设计工具包SystemBuilder设计MPEG4解码器系统的案例研究。我们从MPEG4解码器行为的顺序规范开始，并生成一个FPGA实现。为了提高性能，我们在分析器分析结果的基础上对行为描述进行了细化。最后，我们通过流水线硬件实现实现了超过15fps的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A case study on MPEG4 decoder design with SystemBuilder

This paper presents a case study on designing an MPEG4 decoder system using our system-level design toolkit named SystemBuilder. We start with a sequential specification of the MPEG4 decoder behavior and generate an FPGA implementation. In order to improve the performance, we refine the behavioral description based on the analysis result obtained by a profiler. Finally, we achieve over 15fps performance with pipelined hardware implementation.

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2009 International Symposium on VLSI Design, Automation and Test

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