{"title":"用于为谐波抑制混频器提供六个本振信号的分频器","authors":"Donghai Chen, Zhigong Wang, Junliang Wang, Jian Xu, Yiqiang Wu","doi":"10.1109/ICCSN.2015.7296126","DOIUrl":null,"url":null,"abstract":"In this paper, by analysing the requirement of input LO signals sending to a harmonic rejection mixer (HRM), a divider is designed for HRM, which is used to supply six LO quadrature signals with a phase shift of 45° to cancel the 3th and 5th order harmonics. The divider consists of four D flip-flops which is constructed by two master-slave latches, and the highest operating frequency is inversely proportional to the maximum delay path. And it can operate well over a wide range of 800MHz-1.6GHz. This kind of divider can provide output signals with better stability and improve the match characteristic so that the phase error is less than 1°. Because of the small phase error, harmonic rejection 3th and 5th are better than -50dBc. The divider draws a current of 1.2 mA under 1.8-V supply voltage, fabricated in a 0.18-μm CMOS process with a layout area of 0.0273mm2.","PeriodicalId":319517,"journal":{"name":"2015 IEEE International Conference on Communication Software and Networks (ICCSN)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A divider used to provide six local oscillator signals for harmonic rejection mixer\",\"authors\":\"Donghai Chen, Zhigong Wang, Junliang Wang, Jian Xu, Yiqiang Wu\",\"doi\":\"10.1109/ICCSN.2015.7296126\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, by analysing the requirement of input LO signals sending to a harmonic rejection mixer (HRM), a divider is designed for HRM, which is used to supply six LO quadrature signals with a phase shift of 45° to cancel the 3th and 5th order harmonics. The divider consists of four D flip-flops which is constructed by two master-slave latches, and the highest operating frequency is inversely proportional to the maximum delay path. And it can operate well over a wide range of 800MHz-1.6GHz. This kind of divider can provide output signals with better stability and improve the match characteristic so that the phase error is less than 1°. Because of the small phase error, harmonic rejection 3th and 5th are better than -50dBc. The divider draws a current of 1.2 mA under 1.8-V supply voltage, fabricated in a 0.18-μm CMOS process with a layout area of 0.0273mm2.\",\"PeriodicalId\":319517,\"journal\":{\"name\":\"2015 IEEE International Conference on Communication Software and Networks (ICCSN)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Conference on Communication Software and Networks (ICCSN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCSN.2015.7296126\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Conference on Communication Software and Networks (ICCSN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCSN.2015.7296126","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A divider used to provide six local oscillator signals for harmonic rejection mixer
In this paper, by analysing the requirement of input LO signals sending to a harmonic rejection mixer (HRM), a divider is designed for HRM, which is used to supply six LO quadrature signals with a phase shift of 45° to cancel the 3th and 5th order harmonics. The divider consists of four D flip-flops which is constructed by two master-slave latches, and the highest operating frequency is inversely proportional to the maximum delay path. And it can operate well over a wide range of 800MHz-1.6GHz. This kind of divider can provide output signals with better stability and improve the match characteristic so that the phase error is less than 1°. Because of the small phase error, harmonic rejection 3th and 5th are better than -50dBc. The divider draws a current of 1.2 mA under 1.8-V supply voltage, fabricated in a 0.18-μm CMOS process with a layout area of 0.0273mm2.