An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors

This paper describes an approach for tight integration between a synthesis and a placement tool. The purpose of this integration is to improve timing convergence of advanced microprocessors. It is shown that this approach results in "legal" placements with, in general, lower delay, and design size. More significantly, the number of iterations to reach a timing closure is reduced drastically. The wire length estimates that are being used to traditionally drive the timing optimization in synthesis are inadequate. Instead, the integrated approach leads to enhanced results as well as faster timing convergence. The impact of various parameters in synthesis and placement on the final results is shown.