BHDL: B中的电路设计

Third International Conference on Application of Concurrency to System Design, 2003. Proceedings. Pub Date : 2003-06-18 DOI:10.1109/CSD.2003.1207723

A. Aljer, P. Devienne, S. Tison, J. Boulanger, G. Mariano

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引用次数: 11

摘要

本课题的主要目的是提供一种正确设计数字电路的方法。它结合了众所周知的电路设计语言VHDL的优点和B方法的力量，保证了正确的设计(w.r.t.正式规范)。这样可以避免设计测试，因为它是“经过验证的结构正确的”。此外，本项目还提供了一个名为BHDL的工具，该工具具有用于创建、编辑、查看和验证模块化硬件架构的图形界面。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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BHDL: circuit design in B

The main goal of this project is to provide a method of correct design of digital circuit. It combines the advantages of VHDL, the well-known language of circuit design, with the power of B method that guarantees the correct design (w.r.t. a formal specification). This allows avoiding the design test since it is "correct by proven construction". Furthermore, this project provides a tool, called BHDL, with a graphical interface for creating, editing, viewing and proving modular hardware architectures.

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Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.

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