Pattern classification algorithms for real-time image segmentation

Algorithms for use with a previously published VLSI architecture for pattern classification are presented. This architecture is based on the evaluation of class discriminant functions without cross terms. Tradeoffs in architecture design have been required to allow high throughput, and the decision regions in feature space which can be generated using this architecture therefore form a restricted subset of possible decision regions. The properties of such decision regions and associated classifier training algorithms are investigated. Some experimental results are included.<>