A Novel High performance D-latch using Gate Engineered Schottky device

In this paper, we propose and simulate a novel D latch design employing a metal silicide source/drain Schottky structure based Sajad Sunil Schottky (SSS) device. The technology is utilised in the realisation of D latch using split gate technique. Conventional D-latch employs at least 4 NAND gates i.e. 16 MOS transistors for its CMOS implementation which therefore calls for more area as well as consumes more power. The novelty of our design is that it reduces the transistor count that is as low as 3 and thereby enhances the packaging density along with retaining all the benefits of the parent device like elimination of series resistance problem, Low power dissipation, reduced number of junctions and reduction in thermal budget due to inclusion of metal source/drain.