通过阻抗减小和动态电压调度方案实现保护带最小化

2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2018-10-01 DOI:10.1109/EPEPS.2018.8534272

Amit KumarJain, Sameer Shekhar, Chin LeeKuan

{"title":"通过阻抗减小和动态电压调度方案实现保护带最小化","authors":"Amit KumarJain, Sameer Shekhar, Chin LeeKuan","doi":"10.1109/EPEPS.2018.8534272","DOIUrl":null,"url":null,"abstract":"Voltage guard bands required to safeguard against load transient induced voltage undershoots result in power and performance penalties for high performance CPUs. This paper presents design techniques for impedance minimization and framework to dynamically alter sense and reference voltages based on information about distributed impedance, silicon speed, and scheduled load activity. Studies show guard band reduction by several tens of mV.","PeriodicalId":403235,"journal":{"name":"2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Guard Band Minimization via Impedance Reduction and Dynamic Voltage Scheduling Schemes\",\"authors\":\"Amit KumarJain, Sameer Shekhar, Chin LeeKuan\",\"doi\":\"10.1109/EPEPS.2018.8534272\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Voltage guard bands required to safeguard against load transient induced voltage undershoots result in power and performance penalties for high performance CPUs. This paper presents design techniques for impedance minimization and framework to dynamically alter sense and reference voltages based on information about distributed impedance, silicon speed, and scheduled load activity. Studies show guard band reduction by several tens of mV.\",\"PeriodicalId\":403235,\"journal\":{\"name\":\"2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEPS.2018.8534272\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPS.2018.8534272","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

电压保护带需要防止负载瞬态感应电压过低导致高性能cpu的功率和性能损失。本文介绍了阻抗最小化的设计技术，以及基于分布阻抗、硅速度和计划负载活动的信息动态改变感测电压和参考电压的框架。研究表明，保护带减少了几十毫伏。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Guard Band Minimization via Impedance Reduction and Dynamic Voltage Scheduling Schemes

Voltage guard bands required to safeguard against load transient induced voltage undershoots result in power and performance penalties for high performance CPUs. This paper presents design techniques for impedance minimization and framework to dynamically alter sense and reference voltages based on information about distributed impedance, silicon speed, and scheduled load activity. Studies show guard band reduction by several tens of mV.

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来源期刊

2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

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