海报:支持硬件事务性内存的COTS多核处理器上的容错执行

2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) Pub Date : 2016-09-11 DOI:10.1145/2967938.2974051

Florian Haas, Sebastian Weis, T. Ungerer, Gilles A. Pokam, Youfeng Wu

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引用次数: 1

摘要

基于软件的容错机制可以提高多核cpu的可靠性，同时比lockstep架构等硬件解决方案更便宜、更灵活。然而，如果在软件中实现，检查点创建、错误检测和纠正会带来很高的性能开销。我们提出了一种软件/硬件混合方法，它利用英特尔的硬件事务性内存(TSX)来支持隐式检查点创建和快速回滚。提出并评估了硬件增强功能，结果导致平均19%的性能开销。

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POSTER: Fault-tolerant execution on COTS multi-core processors with hardware transactional memory support

Software-based fault-tolerance mechanisms can increase the reliability of multi-core CPUs while being cheaper and more flexible than hardware solutions like lockstep architectures. However, checkpoint creation, error detection and correction entail high performance overhead if implemented in software. We propose a software/hardware hybrid approach, which leverages Intel's hardware transactional memory (TSX) to support implicit checkpoint creation and fast rollback. Hardware enhancements are proposed and evaluated, leading to a resulting performance overhead of 19% on average.

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2016 International Conference on Parallel Architecture and Compilation Techniques (PACT)

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