Synthesis of complex VHDL operators

Behavioral descriptions in VHDL often take advantage of complex operations to describe the behavior of a system in a comprehensive way. Existing synthesis tools, however, are not able to handle the complete set of operations. A time expansive transformation is required to map the high level behavioral description to a lower level description containing only operations that can be processed by synthesis tools. A methodology for replacing a high level mathematical operator with a lower level description is described. In this approach a generator produces synthesizable code able to execute the same function as the original operator. The method allows a design space exploration in time and area. The authors present a multiplier generator to show the benefits of the approach.<>