Effect of High-K Dielectric on the Performances of Adiabatic Logic Circuits in Sub-Threshold Regime

Adiabatic logic style is efficient for the design and implementation of the low power, digital system, with reduced circuit delay. In this paper, effect of high K gate dielectric on the power dissipation and delay of the adiabatic logic circuits in sub-threshold regime for ultra-low power applications have been analysed in depth. Hence Energy Efficient Sub-Threshold Adiabatic Logic (EESAL)has been adopted as reference circuit. Besides, analytic models have been detailed to analyse the impact of temperature, supply voltage, capacitive load and frequency have been detailed for adiabatic logic circuits having different gate dielectric. Extensive SPICE simulations have been done to validate the analytical data. The analysis would be efficacious to choose the selective gate materials for the applications in the low power regime.