{"title":"混合高性能低功耗和超低能耗可靠缓存","authors":"Bojan Maric, J. Abella, F. Cazorla, M. Valero","doi":"10.1145/2016604.2016619","DOIUrl":null,"url":null,"abstract":"Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high voltage to provide high performance and at near-/sub-threshold voltage to provide ultra-low energy consumption.\n This paper studies different non-hybrid and hybrid SRAM L1 cache designs using several SRAM cell types and compare them in terms of delay, dynamic energy, leakage power and area.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"27 11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Hybrid high-performance low-power and ultra-low energy reliable caches\",\"authors\":\"Bojan Maric, J. Abella, F. Cazorla, M. Valero\",\"doi\":\"10.1145/2016604.2016619\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high voltage to provide high performance and at near-/sub-threshold voltage to provide ultra-low energy consumption.\\n This paper studies different non-hybrid and hybrid SRAM L1 cache designs using several SRAM cell types and compare them in terms of delay, dynamic energy, leakage power and area.\",\"PeriodicalId\":430420,\"journal\":{\"name\":\"ACM International Conference on Computing Frontiers\",\"volume\":\"27 11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-05-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ACM International Conference on Computing Frontiers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/2016604.2016619\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM International Conference on Computing Frontiers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2016604.2016619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hybrid high-performance low-power and ultra-low energy reliable caches
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high voltage to provide high performance and at near-/sub-threshold voltage to provide ultra-low energy consumption.
This paper studies different non-hybrid and hybrid SRAM L1 cache designs using several SRAM cell types and compare them in terms of delay, dynamic energy, leakage power and area.