{"title":"在RISC-V内核上执行的程序的代码完整性和控制流验证","authors":"Anthony Zgheib, O. Potin, J. Rigaud, J. Dutertre","doi":"10.1109/HOST55118.2023.10133542","DOIUrl":null,"url":null,"abstract":"Fault Injection Attacks (FIA) are powerful threats that can modify the intended behavior of a program running on a processor. Control Flow Integrity (CFI) is used to check at runtime that a program’s execution path follows its corresponding Control Flow Graph (CFG) and is not altered by these attacks. Recent works have stated that developers do not sufficiently consider hardware specifications while designing software countermeasures. Moreover, most hardware and codesign CFI solutions do not cover the integrity of the processor microarchitecture. This paper presents CIFER, a Code Integrity and control Flow verification system for programs Executed on a RISC-V core. It ensures instruction execution in the core while checking the microarchitectural control signals. This is known as a Control Flow and Execution Integrity (CFEI) approach. Our solution is built upon the RISC-V Trace Encoder (TE) which provides information about the execution path of the user’s program. CIFER proposes an evolution of the TE standard and an analysis of the targeted core’s architecture to monitor the pipeline control signals. The average hardware area overheads of our solution range from 35.2% to 55%. Compared to existing CFI and CFEI countermeasures, CIFER presents no performance costs. It does not modify the RISC-V Instruction Set Architecture (ISA), the compilation process nor the user code.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core\",\"authors\":\"Anthony Zgheib, O. Potin, J. Rigaud, J. Dutertre\",\"doi\":\"10.1109/HOST55118.2023.10133542\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fault Injection Attacks (FIA) are powerful threats that can modify the intended behavior of a program running on a processor. Control Flow Integrity (CFI) is used to check at runtime that a program’s execution path follows its corresponding Control Flow Graph (CFG) and is not altered by these attacks. Recent works have stated that developers do not sufficiently consider hardware specifications while designing software countermeasures. Moreover, most hardware and codesign CFI solutions do not cover the integrity of the processor microarchitecture. This paper presents CIFER, a Code Integrity and control Flow verification system for programs Executed on a RISC-V core. It ensures instruction execution in the core while checking the microarchitectural control signals. This is known as a Control Flow and Execution Integrity (CFEI) approach. Our solution is built upon the RISC-V Trace Encoder (TE) which provides information about the execution path of the user’s program. CIFER proposes an evolution of the TE standard and an analysis of the targeted core’s architecture to monitor the pipeline control signals. The average hardware area overheads of our solution range from 35.2% to 55%. Compared to existing CFI and CFEI countermeasures, CIFER presents no performance costs. It does not modify the RISC-V Instruction Set Architecture (ISA), the compilation process nor the user code.\",\"PeriodicalId\":128125,\"journal\":{\"name\":\"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOST55118.2023.10133542\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOST55118.2023.10133542","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core
Fault Injection Attacks (FIA) are powerful threats that can modify the intended behavior of a program running on a processor. Control Flow Integrity (CFI) is used to check at runtime that a program’s execution path follows its corresponding Control Flow Graph (CFG) and is not altered by these attacks. Recent works have stated that developers do not sufficiently consider hardware specifications while designing software countermeasures. Moreover, most hardware and codesign CFI solutions do not cover the integrity of the processor microarchitecture. This paper presents CIFER, a Code Integrity and control Flow verification system for programs Executed on a RISC-V core. It ensures instruction execution in the core while checking the microarchitectural control signals. This is known as a Control Flow and Execution Integrity (CFEI) approach. Our solution is built upon the RISC-V Trace Encoder (TE) which provides information about the execution path of the user’s program. CIFER proposes an evolution of the TE standard and an analysis of the targeted core’s architecture to monitor the pipeline control signals. The average hardware area overheads of our solution range from 35.2% to 55%. Compared to existing CFI and CFEI countermeasures, CIFER presents no performance costs. It does not modify the RISC-V Instruction Set Architecture (ISA), the compilation process nor the user code.