基于相位的单比特Delta-Sigma ADC架构

2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI:10.1109/NEWCAS.2011.5981256

Yiqiao Lin, D. Liao, C. Hung, M. Ismail

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引用次数: 2

摘要

提出了一种基于相位的Delta-Sigma (ΔΣ)模数转换器(ADC)，采用延迟锁环(DLL)机制。它是通过在反馈路径中使用基于电压控制延迟线(VCDL)的量化器和电荷泵对DLL进行修改来实现的。该结构提供了参考抖动整形和量化噪声整形。仿真结果表明，在10mhz信号带宽下，ΔΣ ADC的分辨率为7.99位，OSR =32。

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A phase-based single-bit Delta-Sigma ADC architecture

A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ΔΣ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.

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2011 IEEE 9th International New Circuits and systems conference

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