{"title":"一种用于可预测实时嵌入式系统的动态刮记板存储单元","authors":"Saud Wasly, R. Pellizzoni","doi":"10.1109/ECRTS.2013.28","DOIUrl":null,"url":null,"abstract":"Scratchpad memory is an attractive alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However, dynamic management of scratchpad content is challenging in multitasking environments. To address this issue, we propose the design of a novel Real-Time Scratchpad Memory Unit (RSMU). Our RSMU can be integrated in existing systems with minimal architectural modifications. Furthermore, scratchpad management is performed at the OS level, requiring no application changes. Compared to existing multitasking scratchpad management schemes, our approach improves schedulability by hiding the latency of memory transfers. We demonstrate and evaluate our system design on an embedded FPGA platform.","PeriodicalId":247550,"journal":{"name":"2013 25th Euromicro Conference on Real-Time Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":"{\"title\":\"A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems\",\"authors\":\"Saud Wasly, R. Pellizzoni\",\"doi\":\"10.1109/ECRTS.2013.28\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Scratchpad memory is an attractive alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However, dynamic management of scratchpad content is challenging in multitasking environments. To address this issue, we propose the design of a novel Real-Time Scratchpad Memory Unit (RSMU). Our RSMU can be integrated in existing systems with minimal architectural modifications. Furthermore, scratchpad management is performed at the OS level, requiring no application changes. Compared to existing multitasking scratchpad management schemes, our approach improves schedulability by hiding the latency of memory transfers. We demonstrate and evaluate our system design on an embedded FPGA platform.\",\"PeriodicalId\":247550,\"journal\":{\"name\":\"2013 25th Euromicro Conference on Real-Time Systems\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-07-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"36\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 25th Euromicro Conference on Real-Time Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECRTS.2013.28\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 25th Euromicro Conference on Real-Time Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECRTS.2013.28","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems
Scratchpad memory is an attractive alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However, dynamic management of scratchpad content is challenging in multitasking environments. To address this issue, we propose the design of a novel Real-Time Scratchpad Memory Unit (RSMU). Our RSMU can be integrated in existing systems with minimal architectural modifications. Furthermore, scratchpad management is performed at the OS level, requiring no application changes. Compared to existing multitasking scratchpad management schemes, our approach improves schedulability by hiding the latency of memory transfers. We demonstrate and evaluate our system design on an embedded FPGA platform.