A low cost, low power AES ASIC with high DPA resisting ability

THUAES06 that implements the standard AES algorithm is characterized by low cost, low power and high differential power analysis (DPA) resisting ability enhancement. The DPA resisting ability enhancement is achieved by using fine grained shuffling as the DPA countermeasure of the main part and implementing vulnerable function unit with dual rail asynchronous circuits. THUAES06 is implemented in SMIC 0.18 μm technology. Its average energy of encrypting or decrypting one 128 bits plaintext or cipher text is 19nJ if initial key need not be changed. Its core area is 0.43mm2. The power traces needed to disclose the secrete keys are more than 33,000.