Design of an Efficient Memristor-based Dynamic Exclusive-OR gate.

In this paper, an efficient memristor-based dynamic logic design for an Exclusive-OR gate is proposed. The proposed realization reduces the number of cascaded stages and component count thereby providing an overall performance improvement. The performance of the proposed design is compared with the most recent existing design through LTspice software simulations at 32 nm technology node in terms of total power consumption, average propagation delay, and number of components used in the implementation. The outcomes depict that the proposed design consumes 57 % reduced power and provides faster operation with 5.09 % improvement in propagation delay in comparison to its existing counterpart. Further, the robustness of the proposed design is verified by performing technology and capacitance variation. The results show the impeccable performance of proposed design across different load capacitance and technology nodes.