Giyoung Yang, Hakchul Jung, J. Lim, Jaewoo Seo, Ingyum Kim, Jisun Yu, H. You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, W. Rim, Hayoung Kim, Dalhee Lee, S. Baek, Jonghoon Jung, T. Song, J. Kye
{"title":"基于先进MOL技术的3nm GAA制程标准电池设计优化","authors":"Giyoung Yang, Hakchul Jung, J. Lim, Jaewoo Seo, Ingyum Kim, Jisun Yu, H. You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, W. Rim, Hayoung Kim, Dalhee Lee, S. Baek, Jonghoon Jung, T. Song, J. Kye","doi":"10.1109/vlsitechnologyandcir46769.2022.9830450","DOIUrl":null,"url":null,"abstract":"In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P–N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P–N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P–N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process\",\"authors\":\"Giyoung Yang, Hakchul Jung, J. Lim, Jaewoo Seo, Ingyum Kim, Jisun Yu, H. You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, W. Rim, Hayoung Kim, Dalhee Lee, S. Baek, Jonghoon Jung, T. Song, J. Kye\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830450\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P–N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P–N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P–N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830450\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process
In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P–N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P–N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P–N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.