完全集成超低功耗900 MHz射频收发器,用于无电池无线微系统

Chelho Chung, Young-Han Kim, Tae-Hun Ki, Kyusung Bae, Jongbae Kim
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引用次数: 10

摘要

本文设计了一种超低功耗900 MHz射频收发器集成电路,该集成电路从900 MHz射频载波中获取能量。IC的最小读操作功率灵敏度为−17dbm。模拟功能模块、数字基带和存储系统在0.8 V ~ 2.0 V供电电压范围内工作,不需要电压调节器。只有电流匮乏的环形振荡器工作0.6 V与校准。大部分模拟模块采用低功耗亚阈值工作设计。存储系统选用512位的Fowler-Nordheim隧道非易失性存储器(NVM)。数字基带被设计成时钟门控、时钟恢复、平衡功率分配和自适应功耗方法。收发器IC采用0.18 μm CMOS技术实现。在0.8 V电源电压下,设计的集成电路的总功耗仅为2.64 μW。芯片尺寸为0.65 mm × 0.65 mm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fully integrated ultra-low-power 900 MHz RF transceiver for batteryless wireless microsystems
This paper presents a ultra low power 900 MHz RF transceiver IC. The IC harvests energy from 900 MHz RF carrier wave. The IC has −17 dBm minimum read operation power sensitivity. Analog function blocks, a digital baseband, and a memory system operate with 0.8 V ∼ 2.0 V supply voltage range without voltage regulator. Only current-starved ring oscillator operates 0.6 V with calibration. Most of analog blocks adopted low power subthreshold operating design. The memory system is chosen 512-bit Fowler-Nordheim tunneling non volatile memory (NVM). Digital baseband is designed to clock gating, clock recovery, balanced power distribution, and adaptive power consumption methodology. The transceiver IC is implemented in the 0.18-μm CMOS technology. The overall power consumption of designed IC is only 2.64 μW at 0.8 V supply voltage. The chip size is 0.65 mm × 0.65 mm.
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