Highly Parallel Realization of Sparse Distributed Memory System

A highly parallel realization of Kanerva 's Sparse Distributed Memory has been developed using advanced structures. The system consists of a host computer, address unit and memory unit. The address and memory units have been implemented with commercially available digital components to two functioning boards, and they perform the Hamming distance comparison and memory storage functions. In ordeT to achieve an effective hardware realization the units are designed for highly parallel processing. The host computer i s used to edit, compile, and down-load the programs to be run in the units. The software environment has been implemented under UNIX operating system, and the set of specific commands has been designed to support simulations. The system is intended for real-time applications. The performance estimations are also presented.