{"title":"用于以太网交换的可扩展和完全分布式架构","authors":"M. Herbert, P. Primet, B. Tourancheau, L. Lefèvre","doi":"10.1109/HPSR.2002.1024242","DOIUrl":null,"url":null,"abstract":"We propose a new scalable et flexible architecture for Ethernet switching. First we identify the legacy bottlenecks in classical Ethernet backbones: mainly the tree topology and the redundant packet forwarding decisions. Then we describe how a fully distributed communication architecture, based on proven, high-performance computing concepts (source routing, multistage interconnection, wormhole switching) can provide a scalable backbone inside, with Ethernet compatibility outside. Thanks to carefully placed intelligence, materialized as \"network processors\", we show that not only scalability is enhanced but also flexibility and global transistor count. We present a prototype of this architecture implemented with Myrinet technology.","PeriodicalId":180090,"journal":{"name":"Workshop on High Performance Switching and Routing, Merging Optical and IP Technologie","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A scalable and fully distributed architecture for Ethernet switching\",\"authors\":\"M. Herbert, P. Primet, B. Tourancheau, L. Lefèvre\",\"doi\":\"10.1109/HPSR.2002.1024242\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a new scalable et flexible architecture for Ethernet switching. First we identify the legacy bottlenecks in classical Ethernet backbones: mainly the tree topology and the redundant packet forwarding decisions. Then we describe how a fully distributed communication architecture, based on proven, high-performance computing concepts (source routing, multistage interconnection, wormhole switching) can provide a scalable backbone inside, with Ethernet compatibility outside. Thanks to carefully placed intelligence, materialized as \\\"network processors\\\", we show that not only scalability is enhanced but also flexibility and global transistor count. We present a prototype of this architecture implemented with Myrinet technology.\",\"PeriodicalId\":180090,\"journal\":{\"name\":\"Workshop on High Performance Switching and Routing, Merging Optical and IP Technologie\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Workshop on High Performance Switching and Routing, Merging Optical and IP Technologie\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HPSR.2002.1024242\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Workshop on High Performance Switching and Routing, Merging Optical and IP Technologie","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR.2002.1024242","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A scalable and fully distributed architecture for Ethernet switching
We propose a new scalable et flexible architecture for Ethernet switching. First we identify the legacy bottlenecks in classical Ethernet backbones: mainly the tree topology and the redundant packet forwarding decisions. Then we describe how a fully distributed communication architecture, based on proven, high-performance computing concepts (source routing, multistage interconnection, wormhole switching) can provide a scalable backbone inside, with Ethernet compatibility outside. Thanks to carefully placed intelligence, materialized as "network processors", we show that not only scalability is enhanced but also flexibility and global transistor count. We present a prototype of this architecture implemented with Myrinet technology.