COLUMNUS-an architecture for multi-spin-coding algorithms

In order to improve performance when large systems of simple discrete variables are simulated on general-purpose-computers, multi-spin-coding algorithms have been developed. In this paper, a new architecture is proposed which exploits that kind of SIMD parallelism to a high degree using a large array of cheap memory chips which is directly connected to an army of bit-sequential processors. As each processor can perform different operations simultaneously on the incoming bits, an SIMD*MISD architecture for bit operations results. Many applications including lattice-oriented spin simulations and attractor neural network are presented and discussed for efficiency on this structure. As neural network simulations can be largely accelerated by restricting operations to flipped spins, special hardware is suggested which allows the generation of their indices at a maximum rate.<>