基于CORDIC算法的14位DDS电路设计

2019 IEEE International Conference of Intelligent Applied Systems on Engineering (ICIASE) Pub Date : 2019-04-01 DOI:10.1109/ICIASE45644.2019.9074119

Yali Su, Zejie Kuang, Guohe Zhang, Li Sun

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引用次数: 0

摘要

本文讨论了一种高性能直接数字合成器的硬件电路设计。通过对相位幅度转换模块、输出截断误差处理模块、多位DAC兼容和相位累加器的合理设计，提出了一种基于CORDIC(Coordinate Rotation Digital Computer)算法的14位DDS电路，该电路采用中芯0.13um技术。与查找表方法相比，可以实现更高的速度性能。FPGA实验结果表明，工作频率为200MHz的电路消耗约43320个等效门，频率分辨率达到0.0466 Hz。520MHz工作频率的电路消耗约64520个等效门，频率分辨率为0.121 Hz。SFDR约为112dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 14-bit DDS Circuit Design Based on CORDIC Algorithm

A hardware circuit design for high performance DDS(Direct Digital Synthesizer) is discussed here. With proper design of the phase amplitude conversion module, the output truncation error processing module, multi-bits DAC compatibility and phase accumulator, a 14-bit DDS circuit with SMIC 0.13um technology is presented based on CORDIC(Coordinate Rotation Digital Computer) algorithm. Compared with the lookup table method, higher speed performance can be achieved. The FPGA experiment results show that the circuit with operation frequency 200MHz consumes about 43320 equivalent gates and the frequency resolution reaches 0.0466 Hz. The circuit with 520MHz working frequency consumes about 64520 equivalent gates, while the frequency resolution is 0.121 Hz. And SFDR is about 112dB.

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来源期刊

2019 IEEE International Conference of Intelligent Applied Systems on Engineering (ICIASE)

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