A Load Balance Routing Method with Virtual Escape Network for Network-on-Chip

While virtual channels (VCs) have been used in Network-on-Chip (NoC), the unbalance load in NoC causes the network communication problem, e.g. increasing overhead. In this paper, we propose a novel routing method to balance the network load without changing the router structure. In the proposed routing method, data packets waiting too long in the router use the escape network to accelerate transmission under high data injection rate. We have implemented our design on the XC6VLX240T FPGA using Verilog HDL to evaluate and analyze the routing method. The evaluation results show the proposed design can improve the network communication performance including the transmission latency and throughput under high network load, compared to the conventional mesh-based NoC.