Design of level converters standard cells for circuits with clustered voltage scaling

As technology sizes shrink, the developers come upon a problem of static power. Among the different power reduction approaches with multi voltage there are, which can significantly eliminate components of power consumption on system level. But this methods isn't applicable for implementation within functional units. We are considering issues of practical realization such well-known low-level technique as clustered voltage scaling (CVS). We examine six different variants of level converters (LC) and combined flip-flop level converter (LCFF). All presented variants can achieve power reduction in practical implementation of CVS. Obtained experimental results show that proposed LCFF based on pass transistor logic can be reduce delay from 27 to 51% compared to standard LCs without penalty in power consumption.