{"title":"基于低功耗翻转电压从动器差分对的和级OTA的设计与实现","authors":"Km. Jyotsana, Amit Kumar","doi":"10.1109/GCAT55367.2022.9971883","DOIUrl":null,"url":null,"abstract":"A bulk driven differential pair-based on OTAs with flipped, voltage flowers. Operational transconductance amplifiers (OTAs) for audio frequency applications are used in the signal stage. This article presents a simple and high performance conventional circuit for LP or LV efficient gates as well as a bulk-driven differential pair OTA (DPOTA) for applications of audio frequency. A composite transistor of the (FVFDP) flipped voltage follower differential pair is used to implement the summing stage, so it is capable of building the complete input as well as output dynamic range of (-VSS to VDD), which benefits the (FFV) bulk-driven OTAs of the inpu stage. Along with the design of the proposed OTAs is suitable for the operation of the CMOS transistor used to enhance the DC gain of the (FFV). OTAs, which is reduced the input referred to as noise (IRN) from $\\mathbf{0}.\\mathbf{449}\\boldsymbol{\\mu}\\mathbf{v}/\\mathbf{sqrt}$ (Hz) to 44.49nv/sqrt(Hz) at 100KHz. The transistor-level simulations performed using a 90nm CMOS process conform to the theoretical results of a cadence virtuoso environment. Simulated from a (0.7v to −0.7v) supply. These proposed conventional topology of the OTAs using an (SD) or source degenerative, resistor of 1k succeeds an open loop gain of 76.787 dB, it is seen the unity gain frequency (UGF) of 1.89 kHz and a phase margin of 78.07 companion capacitors is employed, gain bandwidth 14.04 kHz performed consumes at only 130.6nw of power.","PeriodicalId":133597,"journal":{"name":"2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and Implementation of Low Power Flipped Voltage Follower Differential Pair-based Summing Stage OTA\",\"authors\":\"Km. Jyotsana, Amit Kumar\",\"doi\":\"10.1109/GCAT55367.2022.9971883\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A bulk driven differential pair-based on OTAs with flipped, voltage flowers. Operational transconductance amplifiers (OTAs) for audio frequency applications are used in the signal stage. This article presents a simple and high performance conventional circuit for LP or LV efficient gates as well as a bulk-driven differential pair OTA (DPOTA) for applications of audio frequency. A composite transistor of the (FVFDP) flipped voltage follower differential pair is used to implement the summing stage, so it is capable of building the complete input as well as output dynamic range of (-VSS to VDD), which benefits the (FFV) bulk-driven OTAs of the inpu stage. Along with the design of the proposed OTAs is suitable for the operation of the CMOS transistor used to enhance the DC gain of the (FFV). OTAs, which is reduced the input referred to as noise (IRN) from $\\\\mathbf{0}.\\\\mathbf{449}\\\\boldsymbol{\\\\mu}\\\\mathbf{v}/\\\\mathbf{sqrt}$ (Hz) to 44.49nv/sqrt(Hz) at 100KHz. The transistor-level simulations performed using a 90nm CMOS process conform to the theoretical results of a cadence virtuoso environment. Simulated from a (0.7v to −0.7v) supply. These proposed conventional topology of the OTAs using an (SD) or source degenerative, resistor of 1k succeeds an open loop gain of 76.787 dB, it is seen the unity gain frequency (UGF) of 1.89 kHz and a phase margin of 78.07 companion capacitors is employed, gain bandwidth 14.04 kHz performed consumes at only 130.6nw of power.\",\"PeriodicalId\":133597,\"journal\":{\"name\":\"2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GCAT55367.2022.9971883\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCAT55367.2022.9971883","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Implementation of Low Power Flipped Voltage Follower Differential Pair-based Summing Stage OTA
A bulk driven differential pair-based on OTAs with flipped, voltage flowers. Operational transconductance amplifiers (OTAs) for audio frequency applications are used in the signal stage. This article presents a simple and high performance conventional circuit for LP or LV efficient gates as well as a bulk-driven differential pair OTA (DPOTA) for applications of audio frequency. A composite transistor of the (FVFDP) flipped voltage follower differential pair is used to implement the summing stage, so it is capable of building the complete input as well as output dynamic range of (-VSS to VDD), which benefits the (FFV) bulk-driven OTAs of the inpu stage. Along with the design of the proposed OTAs is suitable for the operation of the CMOS transistor used to enhance the DC gain of the (FFV). OTAs, which is reduced the input referred to as noise (IRN) from $\mathbf{0}.\mathbf{449}\boldsymbol{\mu}\mathbf{v}/\mathbf{sqrt}$ (Hz) to 44.49nv/sqrt(Hz) at 100KHz. The transistor-level simulations performed using a 90nm CMOS process conform to the theoretical results of a cadence virtuoso environment. Simulated from a (0.7v to −0.7v) supply. These proposed conventional topology of the OTAs using an (SD) or source degenerative, resistor of 1k succeeds an open loop gain of 76.787 dB, it is seen the unity gain frequency (UGF) of 1.89 kHz and a phase margin of 78.07 companion capacitors is employed, gain bandwidth 14.04 kHz performed consumes at only 130.6nw of power.