A Fully-Connected and Area-Efficient Ising Model Annealing Accelerator for Combinatorial Optimization Problems

The combinatorial optimization problem is ubiquitously in our daily life and typically inefficient for modern Von Neumann architecture-based computer. Targeting for various combinatorial optimization problems, this paper presents a 10K-bit area-efficient architecture of the domain specific accelerator based on fully-connected Ising model using an FPGA platform. The proposed system is based on simulated annealing algorithm with a spin preselection scheme to prevent the system to be trapped in the local minimum and increase the convergence efficiency, which is more easily and efficiently to be hardware implemented. Using max-cut problem as the experiment benchmark, the proposed hardware architecture achieves an acceleration of 50,000 × compared with the software simulation result.