M. Ramadan, Brian Dillon, Michael Green, C. Progler, Y. Ham, Ahmad Syukri
{"title":"基于模型的EUV掩模过程校正","authors":"M. Ramadan, Brian Dillon, Michael Green, C. Progler, Y. Ham, Ahmad Syukri","doi":"10.1117/12.2601855","DOIUrl":null,"url":null,"abstract":"Mask process correction (MPC) played a key part improving yield in 14 nm technology node and below using deep ultraviolet lithography (DUVL). Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7 nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern layers at aggressive pitch using a single exposure. Mask critical dimension targeting was found to be a critical factor for yielding wafer process, MPC will be necessary to correct for mask process errors. This paper will focus on building MPC models for EUV mask processes exposed on a variable shape beam lithography tool.","PeriodicalId":138407,"journal":{"name":"Photomask Japan","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Model based mask process correction for EUV Mask\",\"authors\":\"M. Ramadan, Brian Dillon, Michael Green, C. Progler, Y. Ham, Ahmad Syukri\",\"doi\":\"10.1117/12.2601855\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Mask process correction (MPC) played a key part improving yield in 14 nm technology node and below using deep ultraviolet lithography (DUVL). Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7 nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern layers at aggressive pitch using a single exposure. Mask critical dimension targeting was found to be a critical factor for yielding wafer process, MPC will be necessary to correct for mask process errors. This paper will focus on building MPC models for EUV mask processes exposed on a variable shape beam lithography tool.\",\"PeriodicalId\":138407,\"journal\":{\"name\":\"Photomask Japan\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Photomask Japan\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1117/12.2601855\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Photomask Japan","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.2601855","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Mask process correction (MPC) played a key part improving yield in 14 nm technology node and below using deep ultraviolet lithography (DUVL). Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7 nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern layers at aggressive pitch using a single exposure. Mask critical dimension targeting was found to be a critical factor for yielding wafer process, MPC will be necessary to correct for mask process errors. This paper will focus on building MPC models for EUV mask processes exposed on a variable shape beam lithography tool.