A class AB CMOS fully balanced signal generator

In this paper a novel single input to fully balanced output circuit (SFC) is proposed. The circuit operates in a class AB mode to achieve low standby power dissipation and high current drive capability. The circuit produces two buffered balanced output signals without requiring common mode feedback circuit. Measurement results from a 1.2 /spl mu/m N-well CMOS chip indicate a bandwidth of 5.5 MHz while driving a 40 pF load with a supply voltage of /spl plusmn/1.5 V. The circuit is capable of supplying more than 3 mA of output current while consuming 1.1 mW of standby power. The THD is less than -55 dB at 1 KHz and the phase error is less than 2/sup a/ for frequencies up to 1 MHz.