20.6 A 0.5V-VIN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor

In today's system-on-chip designs, a low-drop-out voltage regulator (LDO) is one of the most popular choices to create a distinct voltage domain owing to its high power density. Many LDOs, however, need a large output capacitor (COUT) to compensate a fast load current (ILOAD) change, increasing the number of pins and off-chip components. In synchronous digital LDO designs, high frequency can miniaturize COUT, but it inevitably causes power inefficiency [2]. A recent work has instead employed an event-driven (ED) control scheme to alleviate the COUT requirement, demonstrating a 400µA-class digital LDO with a COUT of 400pF [1]. The ED scheme is promising, but it is still desirable to develop an LDO which can support a larger ILOAD with a smaller COUT. This is indeed a daunting challenge since a substantial reduction in feedback latency (TLAT) is necessary to retain the same level of output voltage change (ΔVOUT) with a smaller COUT. In this work, to shorten latency, we propose to infuse fine-grained parallelism into ED control systems and develop a fully integrated digital LDO. The prototyped LDO can support 1.44mA ILOAD at 0.5V VIN, 0.45V VSP, and 99.2% peak current efficiency. The LDO shows less than 34mV (7.6%) ΔVOUT with a 0.1nF COUT when ΔILOAD is ±1.44mA.