一种基于灰码的时间-数字转换器结构及其FPGA实现

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Pub Date : 2015-08-01 DOI:10.1109/RFIT.2015.7377926

Congbing Li, Haruo Kobayashi

{"title":"一种基于灰码的时间-数字转换器结构及其FPGA实现","authors":"Congbing Li, Haruo Kobayashi","doi":"10.1109/RFIT.2015.7377926","DOIUrl":null,"url":null,"abstract":"A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-free characteristics. Its proof-of-concept prototype was implemented on FPGA, and the measurement and simulation results validate the effectiveness of the proposed architecture.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A gray code based time-to-digital converter architecture and its FPGA implementation\",\"authors\":\"Congbing Li, Haruo Kobayashi\",\"doi\":\"10.1109/RFIT.2015.7377926\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-free characteristics. Its proof-of-concept prototype was implemented on FPGA, and the measurement and simulation results validate the effectiveness of the proposed architecture.\",\"PeriodicalId\":422369,\"journal\":{\"name\":\"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIT.2015.7377926\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2015.7377926","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

提出了一种基于格雷码的无故障时数转换器(TDC)。与闪存型TDC相比，这种架构可以显著减少硬件、功耗和芯片面积，同时保持相当的性能和无故障特性。在FPGA上实现了概念验证原型，测量和仿真结果验证了该架构的有效性。

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A gray code based time-to-digital converter architecture and its FPGA implementation

A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-free characteristics. Its proof-of-concept prototype was implemented on FPGA, and the measurement and simulation results validate the effectiveness of the proposed architecture.

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来源期刊

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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