D. Cordova, P. Toledo, H. Klimach, S. Bampi, E. Fabris
{"title":"一个90db PSRR, 4dbm耐EMI的mosfet基准电压","authors":"D. Cordova, P. Toledo, H. Klimach, S. Bampi, E. Fabris","doi":"10.1109/LASCAS.2016.7451012","DOIUrl":null,"url":null,"abstract":"Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/° C, for the temperature range from -55 to 125 ° C. An EMI source of 4 dBm (1 Vpp) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of -0.17 % and 822 μVpp, respectively.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference\",\"authors\":\"D. Cordova, P. Toledo, H. Klimach, S. Bampi, E. Fabris\",\"doi\":\"10.1109/LASCAS.2016.7451012\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/° C, for the temperature range from -55 to 125 ° C. An EMI source of 4 dBm (1 Vpp) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of -0.17 % and 822 μVpp, respectively.\",\"PeriodicalId\":129875,\"journal\":{\"name\":\"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LASCAS.2016.7451012\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2016.7451012","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference
Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/° C, for the temperature range from -55 to 125 ° C. An EMI source of 4 dBm (1 Vpp) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of -0.17 % and 822 μVpp, respectively.