封装中配电网与片上电感的电磁耦合

Bing-Heng Li, Yan Li, Erping Li
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摘要

随着电子器件工作频率的迅速提高,电磁干扰(EMI)在集成电路领域受到越来越多的关注。本文讨论了封装中配电网络(PDN)与片上电感器之间的电磁耦合机制。采用全波仿真软件CST获取噪声电压。对于对称放置的两个电感,电感感应到的极性相反的两个电压的幅值不相等,因此PDN上存在一个净电压。为了降低噪声电压,提出了两种方法。设计双电源双地PDN (DSDG)可使噪声电压降低86.3%。在电感下第1层刻蚀金属层可使噪声电压降低35.0%,第1、2层刻蚀金属层可使噪声电压降低72.9%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Electromagnetic Coupling between Power Distribution Network and On-chip Inductors in Package
Electromagnetic interference (EMI) is a growing concern in integrated circuits as the operating frequency of electronic devices increases rapidly. In this paper, the electromagnetic coupling mechanism between the power distribution network (PDN) and on-chip inductors in the package is discussed. The full-wave simulation software CST is employed to obtain noise voltages. For the two inductors placed symmetrically, the amplitudes of two voltages with opposite polarity induced by the inductors are not equal, so there is a net voltage on the PDN. In order to reduce the noise voltage, two approaches have been proposed. Designing the PDN with dual supply voltages and dual grounds (DSDG) can reduce the noise voltage by 86.3%. And etching metal layer 1st under the inductors can reduce the noise voltage by 35.0% while etching metal layers 1st, 2nd can reduce the noise voltage by 72.9%.
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