容错自定时电路

A. Zatsarinny, Y. Stepchenkov, Y. Diachenko, Yury Rogdestvenski, L. Plekhanov
{"title":"容错自定时电路","authors":"A. Zatsarinny, Y. Stepchenkov, Y. Diachenko, Yury Rogdestvenski, L. Plekhanov","doi":"10.29003/m3103.mmmsec-2022/176-178","DOIUrl":null,"url":null,"abstract":"The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to faults. Redundant ST coding and two-phase discipline ensures that ST circuits are more tolerant to the faults than synchronous counterparts. Duplicating ST channels instead of tripling reduces redundancy of the fault-tolerant ST circuits and retains their reliability level compared to synchronous counterparts","PeriodicalId":151453,"journal":{"name":"Mathematical modeling in materials science of electronic component","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FAULT-TOLERANT SELT-TIMED CIRCUITS\",\"authors\":\"A. Zatsarinny, Y. Stepchenkov, Y. Diachenko, Yury Rogdestvenski, L. Plekhanov\",\"doi\":\"10.29003/m3103.mmmsec-2022/176-178\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to faults. Redundant ST coding and two-phase discipline ensures that ST circuits are more tolerant to the faults than synchronous counterparts. Duplicating ST channels instead of tripling reduces redundancy of the fault-tolerant ST circuits and retains their reliability level compared to synchronous counterparts\",\"PeriodicalId\":151453,\"journal\":{\"name\":\"Mathematical modeling in materials science of electronic component\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Mathematical modeling in materials science of electronic component\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.29003/m3103.mmmsec-2022/176-178\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Mathematical modeling in materials science of electronic component","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.29003/m3103.mmmsec-2022/176-178","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文考虑了开发可容错的同步和自定时电路的问题。冗余ST编码和两相原则确保ST电路比同步对应物更能容忍故障。复制ST通道而不是三倍减少了容错ST电路的冗余,并保持了与同步对口电路相比的可靠性水平
本文章由计算机程序翻译,如有差异,请以英文原文为准。
FAULT-TOLERANT SELT-TIMED CIRCUITS
The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to faults. Redundant ST coding and two-phase discipline ensures that ST circuits are more tolerant to the faults than synchronous counterparts. Duplicating ST channels instead of tripling reduces redundancy of the fault-tolerant ST circuits and retains their reliability level compared to synchronous counterparts
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