Area Efficient Nearly Accurate Approximate Adder Design

As CMOS technology is scaling down day by day to a few nanometre, there is a difficulty in improving circuit performance and energy scaling in a cost-effective manner. On the other hand, computational scaling from future workloads is increasing rapidly, because of this there is a gap between capabilities of CMOS technology scaling down and the requirement for future application workloads. In such scenario, either we have to accept computing systems that are good enough or look for alternative modifications to advance them without technological progress. There are several approaches, which can reduce this gap by improving system capabilities. Approximate computing is one of them. It is now becoming an interesting area for energy efficiency since computing-intensive applications such as visual processing, multimedia signal does not require accuracy to work correctly. In this paper, an approximate adder is proposed which is nearly equal to its accurate counterpart in terms of delay and accuracy. And have improvement in terms, power, and area over 50% when compared to conventional adder's implementation and 10% when compared to existing ones.