收缩阵列测试的时间复杂度

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224373

N. Faroughi

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引用次数: 1

摘要

在不了解细胞功能的情况下，推导了c可测试正交迭代收缩阵列(OISA)的测试时间。测试输入被再生为一些内部细胞的输入，在未来的某个时间，在已知的距离(再生距离)，从那些目前正在被测试的细胞的输出。为了使试验时间最短，要求最后施加再生距离最大的试验输入。对于非oisa，提出了在每个单元中可重构的功能路由器。非oisa可以重新配置为一个或多个oisa。

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Time complexity of systolic array testing

The testing time for a C-testable orthogonal iterative systolic array (OISA) is derived where no knowledge on cell functions are assumed. The test inputs are regenerated as inputs for some inner cells at some future times at known distances (regeneration distances) from the outputs of those cells which are currently being tested. For minimum test time, it is required that the test input with maximum regeneration distance be applied last. For the non-OISAs, reconfigurable functional routers in each cell is proposed. A non-OISA can be reconfigured into one or more OISAs.<>

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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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