A 28Gbps reference-less VCO based CDR with separate proportional path technology in 65nm CMOS

This paper presents a 28Gbps voltage controlled oscillator (VCO) based clock and data recovery (CDR) with a separate proportional path technology. It employs a quarter rate ternary Bang-Bang phase detector to extract the phase error between the local clock and input data. The circuit designed in a 65nm CMOS process achieves ±1000 ppm lock-in rang, ±6000 ppm tracking range. The simulation results show that the total jitter of the recovered clock is 4.7ps when the CDR locked at 28 Gb/s. In addition, this CDR can track a 500 KHz sinusoidal phase jitter with 2UI amplitude.