R. Sakile, A. Bhanuchandar, Kasoju Bharath Kumar, D. Vamshy, Bandela Supriya, Kowstubha Palle
{"title":"基于级联半桥的多电平直流链路逆变器拓扑的最近电平控制方案","authors":"R. Sakile, A. Bhanuchandar, Kasoju Bharath Kumar, D. Vamshy, Bandela Supriya, Kowstubha Palle","doi":"10.1109/SPIN52536.2021.9566056","DOIUrl":null,"url":null,"abstract":"In this paper, a Nearest Level Control (NLC) scheme for Reduced Switch Count (RSC) cascaded half-bridge based Multilevel DC-Link (MLDCL)inverter topology with three different source configurations (1:1:1:1, 1:2:3:4 and 1:2:4:8) have been explained clearly. For generating particular level in the inverter output, NLC technique has been utilized. The NLC technique is generally a low switching frequency technique thereby switching losses are greatly reduces and it is suitable for any kind of inverter topology. The MLDCL topology consists of 8 unidirectional switches in the level generator side, 4 unidirectional switches in the polarity generator side and 4 dc sources. For generating P-level output, only P+3 switches are required then the requirement of gate driver circuits, protection circuits have been reduced. Basically, NLC technique is more suitable for higher level inverter topologies and provides best harmonic performance as compared with conventional Pulse Width Modulation (PWM) techniques. The operation and feasibility of the topology with control scheme have been validated through the MATLAB/Simulink platform.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Nearest Level Control Scheme for Reduced Switch Count Cascaded Half-Bridge Based Multilevel DC Link Inverter Topology\",\"authors\":\"R. Sakile, A. Bhanuchandar, Kasoju Bharath Kumar, D. Vamshy, Bandela Supriya, Kowstubha Palle\",\"doi\":\"10.1109/SPIN52536.2021.9566056\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a Nearest Level Control (NLC) scheme for Reduced Switch Count (RSC) cascaded half-bridge based Multilevel DC-Link (MLDCL)inverter topology with three different source configurations (1:1:1:1, 1:2:3:4 and 1:2:4:8) have been explained clearly. For generating particular level in the inverter output, NLC technique has been utilized. The NLC technique is generally a low switching frequency technique thereby switching losses are greatly reduces and it is suitable for any kind of inverter topology. The MLDCL topology consists of 8 unidirectional switches in the level generator side, 4 unidirectional switches in the polarity generator side and 4 dc sources. For generating P-level output, only P+3 switches are required then the requirement of gate driver circuits, protection circuits have been reduced. Basically, NLC technique is more suitable for higher level inverter topologies and provides best harmonic performance as compared with conventional Pulse Width Modulation (PWM) techniques. The operation and feasibility of the topology with control scheme have been validated through the MATLAB/Simulink platform.\",\"PeriodicalId\":343177,\"journal\":{\"name\":\"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPIN52536.2021.9566056\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN52536.2021.9566056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Nearest Level Control Scheme for Reduced Switch Count Cascaded Half-Bridge Based Multilevel DC Link Inverter Topology
In this paper, a Nearest Level Control (NLC) scheme for Reduced Switch Count (RSC) cascaded half-bridge based Multilevel DC-Link (MLDCL)inverter topology with three different source configurations (1:1:1:1, 1:2:3:4 and 1:2:4:8) have been explained clearly. For generating particular level in the inverter output, NLC technique has been utilized. The NLC technique is generally a low switching frequency technique thereby switching losses are greatly reduces and it is suitable for any kind of inverter topology. The MLDCL topology consists of 8 unidirectional switches in the level generator side, 4 unidirectional switches in the polarity generator side and 4 dc sources. For generating P-level output, only P+3 switches are required then the requirement of gate driver circuits, protection circuits have been reduced. Basically, NLC technique is more suitable for higher level inverter topologies and provides best harmonic performance as compared with conventional Pulse Width Modulation (PWM) techniques. The operation and feasibility of the topology with control scheme have been validated through the MATLAB/Simulink platform.