3D集成是未来可靠计算平台的途径吗?

S. Safiruddin, D. Borodin, M. Lefter, G. Voicu, S. Cotofana
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引用次数: 8

摘要

随着CMOS集成电路技术扩展到22nm以下的范围并面临物理限制,实现可靠的计算系统变得越来越困难。可靠的计算也是各种新技术的主要关注点,这些技术正在被研究以克服CMOS技术的物理限制。虽然3D集成最初是作为一种无需缩放即可实现集成电路加速的方法提出的,但它为可靠的计算提供了许多新的机会。3D集成为设计空间增加了两个新的维度:(i) z维度,因为现在可以将应用程序映射到放置在不同平面上的电路部件上;(ii) r维度,因为可以选择具有不同可靠性的不同平面。这极大地扩展了解决方案空间,并为处理新的和现有的挑战提供了许多机会。在本文中,我们通过探索3D集成提供的机会来确定实现可靠计算的重要策略。我们提出了系统级的方法来减轻潜在的技术可靠性缺陷,并研究了基于tsv的3D集成带来的机会,重点是系统可靠性的观点。我们的研究清楚地表明,所提出的3D可靠计算范式,如果得到发展和进一步探索,可以促进缩小封装尺寸和增加晶体管密度的趋势的延续,并允许成功利用新的新兴的不可靠器件。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Is 3D integration the way to future dependable computing platforms?
Achieving dependable computing systems is becoming increasingly more difficult as CMOS integrated circuits technology scaling reaches sub-22nm ranges and faces physical limitations. Dependable computing is also a major concern with the various new technologies that are being investigated to overcome the physical limitations of CMOS technology. 3D integration, though initially proposed as a way of achieving speedup of integrated circuits without the need for scaling, offers many new opportunities for dependable computing. 3D integration adds two new dimensions to the design space: (i) the z-dimension, as now the application can be mapped on parts of the circuit that are placed in different planes, and (ii) the R-dimension as different planes can be selected with different reliabilities. This greatly expands the solution space and provides many opportunities to deal with new and existing challenges. In this paper we identify important strategies to achieve dependable computing by exploring the opportunities that 3D integration offers. We present systems level approaches for alleviating underlying technology reliability shortcomings and investigate the opportunities opened up by TSV-based 3D integration with emphasis on the system reliability point of view. Our investigation clearly indicates that the proposed 3D dependable computing paradigms, if developed and further explored, can facilitate the continuation of the trend of reducing package size and increasing transistor densities, and allow for the successful utilization of novel emerging unreliable devices.
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