软误差自定时管道抗扰度的改进

2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus) Pub Date : 2021-01-26 DOI:10.1109/ElConRus51938.2021.9396125

Yury Stepchenkov, Yury Rogdestvenski, Yury Shikunov, D. Diachenko, Y. Diachenko

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引用次数: 0

摘要

本文介绍了自定时(ST)数字电路软误差容限的研究结果。实用的ST电路都有流水线结构。ST管道的组合部分自然不受72%的短期软错误的影响。所提出的电路和布局方法将ST管道组合部件的故障容忍度提高到98%以上。ST管道级寄存器最容易产生软误差。基于c -元件的ST管道寄存器位单元的典型变体具有83%的容错率。所提出的寄存器位实现案例将ST管道的容错率提高到98%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improvement of Self-Timed Pipeline Immunity of Soft Errors

The paper presents the results of a study of self-timed (ST) digital circuits' soft-error tolerance. Practical ST circuits have a pipeline structure. The combinational parts of the ST pipeline are naturally immune to 72% of short-term soft errors. The proposed circuitry and layout methods increase the ST pipeline combinational part's failure tolerance to 98% and higher. ST pipeline stage register is the most susceptible to soft errors. A typical variant of the ST pipeline register bit unit based on C-elements has a failure tolerance of 83%. The proposed register bit implementation cases increase the failure tolerance of the ST pipeline up to 98%.

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2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

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