基于水平交叉量化的心房电记录活动相关多通道ADC架构

Aurojyoti Das, Samprajani Rout, A. Urso, W. Serdijn
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引用次数: 1

摘要

提出了一种新的多通道平交ADC结构,用于记录多通道心房电图。该体系结构将同步采样与平交(LC)量化相结合,在同时记录多个通道的情况下实现与活动相关的操作。在提出的体系结构中,量化器进行的比较次数取决于输入信号的活动,比传统的SAR ADC低2-3.3倍。该架构使用一个比较器和一个参考电平,而不是像传统LC adc那样使用两个比较器和两个参考电平。所提出的架构是在VerilogA中建模的,旨在在标准的0.18 um CMOS工艺中实现。MLC ADC同时转换来自4个通道的信号,在1.8 V电源下功耗为9.32 μ W, SFDR为53.33 dB, SNDR为48.96 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Activity Dependent Multichannel ADC Architecture using Level Crossing Quantisation for Atrial Electrogram Recording
This paper presents a novel multichannel level-crossing (MLC) ADC architecture aimed at recording atrial electrograms from multiple channels. The proposed architecture combines synchronous sampling with level-crossing (LC) quantisation to achieve activity dependent operation while recording from multiple channels simultaneously. In the proposed architecture the number of comparisons performed by the quantiser to reach a decision is dependent on the activity of the input signal and is 2-3.3 times lower than that in a conventional SAR ADC. The architecture uses one comparator and one reference level instead of two comparators and two reference levels as in conventional LC ADCs. The proposed architecture is modeled in VerilogA and is designed to be implemented in a standard 0.18 um CMOS process. The MLC ADC converts signals from 4 channels simultaneously and achieves an SFDR of 53.33 dB and an SNDR of 48.96 dB while consuming 9.32 µW of power from a 1.8 V power supply.
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