计算机辅助设计(CAD)信息与缺陷评审SEM平台的集成及基于缺陷自动分类的设计:DI:缺陷检测与减少

T. Esposito, Jay K Shah, Abhinav Jain, F. Levitov, J. G. Sheridan, Shashi Shekhar, S. Jen, V. Aristov, Hoang Nguyen
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引用次数: 2

摘要

先进的FinFET器件的缺陷测量在缺陷审查扫描电子显微镜(DR-SEM)图像的准确分类方面面临着各种挑战。随着感兴趣的缺陷(DOI)尺寸与打印特征尺寸成比例地缩小,这些平台进行调整以继续提供最佳的缺陷分类是至关重要的。通过将计算机辅助设计(CAD)信息引入这些平台,可以最有效地实现这一目标。为了改善DR-SEM中缺陷的成像,使用CAD数据来增强对准步骤,提供更准确的缺陷导航,并允许根据较小的缺陷尺寸缩放放大。我们提出了一种简化的方法,将这种基于CAD的校准步骤引入DR-SEM平台上现有的配方管理系统。虽然减小图像视场是有益的,但在自动缺陷分类(ADC)中引入CAD信息可以提供有价值的缺陷位置信息。基于设计的ADC (DBA)通过提供基于CAD数据(如掩模或工艺步骤)区分缺陷对设备性能的影响的方法来实现这一点。我们介绍了在sub-1x FinFET工艺中,多图像化和外延层的DBA的两个案例研究。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Integration of Computer-Aided Design (CAD) Information into a Defect-Review SEM Platform and Design Based Automatic Defect Classification : DI: Defect Inspection and Reduction
Defect metrology for advanced FinFET devices faces a variety of challenges in terms of accurate classification of Defect Review Scanning Electron Microscopy (DR-SEM) images. As the Defect of Interest (DOI) size shrinks in proportion to the printed feature dimension, it is critical that these platforms adjust to continue to provide the best possible defect classification. This can be achieved most efficiently by introducing Computer-Aided Design (CAD) information into these platforms. In order to improve imaging of defects in DR-SEM, CAD data is used to enhance the alignment step, providing more accurate navigation to defects and allowing the magnification to scale according to the smaller defect size. We present a streamlined method to introduce this CAD based alignment step into the existing recipe management system on the DR-SEM platform. While decreasing image FOV is beneficial, the introduction of CAD information into Automatic Defect Classification (ADC) can provide valuable information on the defect’s location. Design Based ADC (DBA) achieves this by providing the means to differentiate the defect’s impact on device performance based on CAD data such as mask or process step. We present two case studies of DBA on multi- patterning and epi layers in the sub-1x FinFET process.
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