An FPGA-Based Computation-Efficient Convolutional Neural Network Accelerator

Convolution Neural Networks (CNNs) have gained much popularity in computer vision applications. However, CNNs are computationally intensive and hence it is very difficult to implement CNNs in embedded systems. Thus there is a high demand for resource efficient and low delay CNN accelerators. In this work, an FPGA-based CNN accelerator is designed. In the proposed accelerator, the convolution unit is designed using Karatsuba multiplier which reduces the overall resource utilisation and delay of the CNN accelerator. Simulations are performed using Vivado 2016.4 in Verilog HDL and performance parameters are measured on a Xilinx Artix-7 AC701 evaluation board.