下电集成电路内置自检结构

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208128

P. S. Levy

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引用次数: 0

摘要

由逻辑元件组成的内置自检结构通过单独的Test VDD与主电路隔离，使其在IC正常工作时显示为开路。使用单独的Test VDD对主电路进行重新配置，使测试电路在测试模式下运行。当测试VDD被移除时，测试电路将断电并与主机断开连接，从而对IC的正常工作不可见。

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Power-down integrated circuit built-in self-test structures

Built-in self-test structures composed of logic elements are isolated from the host circuitry by means of separate Test VDD, so that it appears as an open circuit during normal operation of the IC. The separate Test VDD is employed to re-configure the host circuit and operate the test circuitry in the test mode. When Test VDD is removed, the test circuit powers down and disconnects from the host becoming invisible to the normal operation of the IC.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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