基于FinFET的低功耗数字电路研究

2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT) Pub Date : 2017-04-01 DOI:10.1109/ICCPCT.2017.8074280

Ashok Kumar Kuna, Kavindra Kandpal, K. R. Teja

{"title":"基于FinFET的低功耗数字电路研究","authors":"Ashok Kumar Kuna, Kavindra Kandpal, K. R. Teja","doi":"10.1109/ICCPCT.2017.8074280","DOIUrl":null,"url":null,"abstract":"This paper presents a design methodology of flip-flops for low power applications using FinFET. It presents an investigation of the basic characteristics of p-FinFETs and n-FinFETs in various configurations. An Inverter, the simplest digital circuit is implemented and extensively studied to understand the concepts of sizing and optimal choice of the configurations. Multiplexer based approach for implementing the flip-flop has been chosen for demonstration. The Predictive Technology Model (PTM) FinFET 32nm library has been used on HSPICE for implementing the designs. The designed flip-flops operates with 0.9V and consumes a power of 11.4 μW.","PeriodicalId":208028,"journal":{"name":"2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An investigation of FinFET based digital circuits for low power applications\",\"authors\":\"Ashok Kumar Kuna, Kavindra Kandpal, K. R. Teja\",\"doi\":\"10.1109/ICCPCT.2017.8074280\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a design methodology of flip-flops for low power applications using FinFET. It presents an investigation of the basic characteristics of p-FinFETs and n-FinFETs in various configurations. An Inverter, the simplest digital circuit is implemented and extensively studied to understand the concepts of sizing and optimal choice of the configurations. Multiplexer based approach for implementing the flip-flop has been chosen for demonstration. The Predictive Technology Model (PTM) FinFET 32nm library has been used on HSPICE for implementing the designs. The designed flip-flops operates with 0.9V and consumes a power of 11.4 μW.\",\"PeriodicalId\":208028,\"journal\":{\"name\":\"2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT)\",\"volume\":\"107 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCPCT.2017.8074280\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCPCT.2017.8074280","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文提出了一种基于FinFET的低功耗触发器设计方法。研究了p- finfet和n- finfet在不同结构下的基本特性。一个逆变器，最简单的数字电路实现和广泛的研究，以了解尺寸和配置的最佳选择的概念。选择基于多路复用器的触发器实现方法进行演示。预测技术模型(PTM) FinFET 32nm库已在HSPICE上用于实现设计。设计的触发器工作电压为0.9V，功耗为11.4 μW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An investigation of FinFET based digital circuits for low power applications

This paper presents a design methodology of flip-flops for low power applications using FinFET. It presents an investigation of the basic characteristics of p-FinFETs and n-FinFETs in various configurations. An Inverter, the simplest digital circuit is implemented and extensively studied to understand the concepts of sizing and optimal choice of the configurations. Multiplexer based approach for implementing the flip-flop has been chosen for demonstration. The Predictive Technology Model (PTM) FinFET 32nm library has been used on HSPICE for implementing the designs. The designed flip-flops operates with 0.9V and consumes a power of 11.4 μW.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT)

自引率

0.00%

发文量